This invention relates generally to semiconductor integrated circuits and more particularly, it relates to a CMOS output buffer circuit which has a significant reduction in ground bounce.
As is well-known in the art, digital logic circuits are widely used in the areas of electronics and computertype equipment. Specifically, one such use of digital logic circuits is to provide an interface function between one logic type (i.e., TTL) of a first integrated circuit device and another logic type (i.e., CMOS) of a second integrated circuit device. An output buffer circuit is an important component for this interface function. The output buffer circuit provides, when enabled, an output signal which is a function of a data input signal received from other logic circuitry of the integrated circuit.
Output buffer circuits typically use a pull-up transistor device and a pull-down transistor device connected in series between first and second external power supply terminal pins. The first power supply terminal pin may be supplied with a positive potential or voltage VCC, which is connected to an internal power supply potential node via a first connection lead having associated package inductance. The second power supply terminal pin may be supplied with a ground potential VSS which is connected to an internal ground potential node via a second connection lead having associated package inductance. The common connection point of the pull-up and pull-down transistor devices defines an internal output node which is further joined to an external output terminal pin via a third connection lead having associated package inductance. The external output terminal pin is used for driving other circuitry on other integrated circuits which may have widely varying capacitive loading effects.
Dependent upon the logic state of the data input signal and an enable signal being in the active state, either the pull-up or pull-down transistor device is quickly turned OFF and the other one of them is turned ON. Such rapid switching OFF and ON of the pull-up and pull-down devices causes sudden surges of current creating what is commonly known as current spikes. As a result, when the internal output node is making a high-to-low transition, oscillation or inductive ringing will appear at the output terminal pin referred to as "ground bounce." This "ground bounce" is defined to be the undershooting of the ground potential followed by a dampening oscillation around it. This is a major problem encountered in designing high speed, output buffer circuits.
Also, during such output switching, charging and discharging currents from the pull-up and pull-down transistor devices will flow through the package inductances of the power supply and ground lines so as to cause inductive noises at the internal power supply potential node and at the internal ground potential node. While it is desired to have large pull-up and pull-down devices for charging or discharging the capacitive loads at high speeds, which is advantageous, this will also cause increased noises on the internal supply and ground lines that are undesirable since they will degrade the output levels (logic "1" and logic ".phi.") causing interface problems among the output buffer circuit and other integrated circuits. Further, in VLSI systems there will be many output buffer circuits which are switching simultaneously. Thus, it is desired that each output buffer circuit cause a minimal amount of noise on the internal supply and ground lines. However, this should be achieved without sacrificing the high speed of operation. In addition, this should be maintained independently of variations in process parameters.
There have been attempts made in the prior art of output buffer design to minimize the ground bounce and the supply and ground noises without sacrificing the needed high-speed of operation. In FIG. 1, there is shown a schematic circuit diagram of a prior art output buffer circuit which includes a staged pull-up means formed of a first plurality of N-channel transistors 2a, 2b and 2c and a staged pull-down means formed of a second plurality of N-channel transistors 3a, 3b and 3c. The input signal is fed to two AND logic gates 4a, 4b whose outputs provide control signals via inverters for driving the pull-up and pull-down means, respectively. Since there is no effective control of the gate-to-source voltage V.sub.GS, there exists the possibility that one of the transistors in either the pull-up or pull-down means will still be turned on when one of the transistors in the pull-down or pull-up means is being turned on, resulting in a cross-over current due to their simultaneous conduction.
In FIG. 2, there is shown a schematic circuit diagram of another of the prior art output buffer circuit which also includes a staged pull-up means formed of two N-channel transistors 5a, 5b connected in parallel and a staged pull-down means formed of two N-channel transistors 6a, 6b connected in parallel. There are provided NAND logic gates 71-7d and NOR logic gates 8a, 8b which are used to turn off and on the transistors in the pull-up and pull-down means in a correct sequence. However, since there is likewise no control of the voltage V.sub.GS, this prior art circuit does not always perform the proper switching sequence of the transistors as it was designed to do.
The present invention controls the gate-to-source voltages applied to the gates of the transistors to be turned on in the pull-up or pull-down driver circuit after all of the transistors in the pull-down or pull-up driver circuit have been turned off. This is achieved by the provision of resistive means connected in series to the gates of certain ones of the transistors in the pull-up and pull-down driver circuit for delaying the turning on of the same.